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Sheet目录3828

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2010 Microchip Technology Inc.

DS70135G-page 131

dsPIC30F4011/4012

19.3

Modes of Operation

The CAN module can operate in one of several

operation modes selected by the user. These modes

include:

Initialization Mode

Disable Mode

Normal Operation Mode

Listen Only Mode

Loopback Mode

Error Recognition Mode

Modes are requested by setting the REQOP<2:0> bits

(C1CTRL<10:8>). Entry into a mode is acknowledged by

monitoring the OPMODE<2:0> bits (C1CTRL<7:5>). The

module will not change the mode and the OPMODE bits

until a change in mode is acceptable, generally during

bus Idle time which is defined as at least 11 consecutive

recessive bits.

19.3.1

INITIALIZATION MODE

In the Initialization mode, the module will not transmit or

receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer will

have access to Configuration registers that are access

restricted in other modes. The module will protect the

user from accidentally violating the CAN protocol

through programming errors. All registers which control

the configuration of the module can not be modified

while the module is online. The CAN module will not be

allowed to enter the Configuration mode while a

transmission is taking place. The Configuration mode

serves as a lock to protect the following registers.

All Module Control Registers

Baud Rate and Interrupt Configuration Registers

Bus Timing Registers

Identifier Acceptance Filter Registers

Identifier Acceptance Mask Registers

19.3.2

DISABLE MODE

In Disable mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity, however, any pending interrupts will

remain and the error counters will retain their value.

If the REQOP<2:0> bits (C1CTRL<10:8>) = 001, the

module will enter the Disable mode. If the module is

active, the module will wait for 11 recessive bits on the

CAN bus, detect that condition as an Idle bus, then

the

disable

command.

When

the

OPMODE<2:0> bits (C1CTRL<7:5>) = 001, that

indicates whether the module successfully went into

Disable mode. The I/O pins will revert to normal I/O

function when the module is in the Disable mode.

The module can be programmed to apply a low-pass

filter function to the C1RX input line while the module

or the CPU is in Sleep mode. The WAKFIL bit

(C1CFG2<14>) enables or disables the filter.

19.3.3

NORMAL OPERATION MODE

Normal

Operation

mode

selected

when

REQOP<2:0> = 000. In this mode, the module is

activated and the I/O pins will assume the CAN bus

functions. The module will transmit and receive CAN

bus messages via the C1TX and C1RX pins.

19.3.4

LISTEN ONLY MODE

If the Listen Only mode is activated, the module on the

CAN bus is passive. The transmitter buffers revert to

the port I/O function. The receive pins remain inputs.

For the receiver, no error flags or Acknowledge signals

are sent. The error counters are deactivated in this

state. The Listen Only mode can be used for detecting

the baud rate on the CAN bus. To use this, it is

necessary that there are at least two further nodes that

communicate with each other.

19.3.5

ERROR RECOGNITION MODE

The module can be set to ignore all errors and receive

any message. In this mode, the data which is in the

message assembly buffer until the time an error

occurred, is copied in the receive buffer and can be

read via the CPU interface.

19.3.6

LOOPBACK MODE

If the Loopback mode is activated, the module will

connect the internal transmit signal to the internal

receive signal at the module boundary. The transmit

and receive pins revert to their port I/O function.

Note:

Typically, if the CAN module is allowed to

transmit in a particular mode of operation

and a transmission is requested immedi-

ately after the CAN module has been

placed in that mode of operation, the

module waits for 11 consecutive recessive

bits on the bus before starting transmission.

If the user switches to Disable mode within

this 11-bit period, then this transmission is

aborted and the corresponding TXABT bit

is set and TXREQ bit is cleared.

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